1. Field of the Invention
The present invention relates to a magnetic memory using a magneto-resistance element as a data storage element as well as a semiconductor integrated circuit device containing such magnetic memory, and particularly to a magnetic memory, which can maintain integrity between write data and storage data or read data.
2. Description of the Background Art
Attention has been given to an MRAM Magnetic Random Access Memory: magnetic memory device) as a storage device, which nonvolatilely stores data with a low power consumption. The MRAM utilizes such a property that magnetization caused within a ferromagnetic material by an externally applied magnetic field resides within the ferromagnetic material even after the externally applied magnetic field is removed. Several elements such as a Giant Magneto-Resistance element (GMR element), a Colossal Magneto-Resistance element (CMR element) and a Tunnel Magneto-Resistance element (TMR element) have been known as data storage elements of memory cells of the MRAM.
A data storage section of the MRAM cell has a structure, in which two magnetic substance layers are stacked with an insulating film in between. One of these two magnetic substance layers is a fixed layer, of which magnetization direction is utilized as a reference magnetization direction, and the magnetization direction of the other magnetic substance layer (free layer) is changed according to storage data. A magnetic resistance value changes depending on match/mismatch between the magnetization directions of these magnetic substances, and accordingly an amount of current flowing through the storage section changes. Data reading is performed by determining the current flowing through the magnetic substance (magnet) layers of the storage section. For data writing, the direction of the current flow is determined according to the storage data, and a magnetic field induced by this current sets the magnetization direction of the magnet layer (free layer) for data storage.
According to tendencies of down-sizing semiconductor integrated circuit devices and of increasing storage capacities thereof, the MRAMs have been also required to have the increased storage capacities. In this case, it is required to arrange the MRAM cells in the memory cell array at a high density. A prior art reference 1 (Japanese Patent Laying-Open No. 2003-168785) discloses a structure, which aims to arrange MRAM cells in a memory cell array at a high density.
In this prior art reference 1, MRAM cells are stacked three-dimensionally, and a read select gate is arranged commonly to a predetermined number of SAM cells aligned in a column direction. The MRAM cells in the stacked structure are arranged symmetrically with respect to a write interconnection line transmitting a write current so that interconnection lines are reduced in number to suppress deterioration in flatness of the multi-layer interconnection structure of the MRAM cells, which may be otherwise caused by increased number of interconnection lines.
In the structure disclosed in the prior art reference 1, the magnetic field of the same intensity is applied to the free layers of the memory cells arranged symmetrically with respect to the write interconnection line for achieving suppression of variations in intensity of the magnetic field in the write operation. In the data write operation, therefore, the writing magnetic fields of the same magnitude are applied to the memory cells arranged symmetrically with respect to the write interconnection line, and a leak magnetic field may invert the data in an unselected memory cell. In the structure of the prior art reference 1, an interconnection line (bit line), which is connected to the free layer, and causes an assisting magnetic field for the writing magnetic field in the data write operation, are likewise arranged symmetrically. In the case where the write interconnection line applies the magnetic fields of the same magnitude to the free layers of the memory cells arranged symmetrically, the magnetic fields applied from the magnetic field assisting interconnection line (bit line) may cause a problem of magnetic disturbance of erroneous writing in an unselected memory cell. In this prior art reference 1, no consideration is given on an influence of the leak magnetic field exerted on adjacent unselected cells in the data write operation.
Prior art references 2 and 3 (Japanese Patent Laying-Open Nos. 2003-123464 and 2003-109374) disclose structures for overcoming the above problem of magnetic disturbance.
The structure of the prior art reference 2 aims to prevent occurrence of such a situation that electrical charges charged on a parasitic capacitance of a write power supply line cause a rushing current when the writing starts, to cause overshoot in a writing current waveform. In this prior art reference 2, program operation time periods are made being overlapping with each other such that a write current is always consumed in an operation of successively writing data. Thereby, the parasitic capacitance of the write current supply is prevented from accumulating excessive charges, and a peak current (rushing current) in the write current is prevented from occurring during the write operation. Although the structure disclosed in the prior art reference 2 may be applied to the mode of writing data successively, this structure likewise causes the peak current in the write current when data of one bit is to be written or data writing is performed once, and thus the problem of magnetic disturbance arises. Further, no consideration is made on an influence exerted on an adjacent memory cell by the magnetic field induced by the writing magnetic field in a period of overlapping of the write currents in by the operation of successively writing data into adjacent memory cells. In this case, therefore, such a problem still arises that the problem of magnetic disturbance due to the magnetic field induced by the write current cannot be reliably overcome.
In the structure of the prior art reference 3, a current driving power of a write current supply is gradually increased over a plurality of steps to reduce a peak current in the write operation, for preventing erroneous writing. In the structure of the prior art reference 3, write current supplies supplying the write current are arranged corresponding to respective write drivers, and amounts of driving currents of the write drivers are commonly adjusted, resulting in an increased circuit occupation area as well as an increased load on control of the write current sources.
A prior art reference 4 (Japanese Patent Laying-Open No. 2003-249629) discloses a structure, in which write word lines for transmitting write currents in a write operation are also used for read bit lines for transmitting read currents in a data read operation, for improving an integration degree of a memory cell array. In this structure of the prior art reference 4, write word lines/read bit lines extending in a row direction are arranged corresponding to the memory cell rows, and are connected to the memory cells in the corresponding rows, respectively. Corresponding to memory cell columns, source lines and write bit lines are arranged. A read gate is arranged commonly to a predetermined number of memory cells arranged in the column direction, and connects the predetermined number of memory cells to a corresponding source line. Each source line is coupled to a ground node via a column select gate. In the data read operation, the column select gate in the selected column turns conductive according to a column address. In the data read operation, a write-word/read-bit line is selected according to a row address signal, and is coupled to a read circuit via a common data bus.
In the data write operation, write currents are supplied to both the write bit line and the write-word/read-bit line to perform data writing.
In the structure disclosed in the prior art reference 4, the read gate is commonly arranged for the plurality of memory cells instead of arranging a read gate for each memory cell for reducing an area occupied by the memory cells. Further, the write word lines are used also as the read bit lines so that the interconnection lines can be reduced in number, to reduce the array area.
In the structure of the prior art reference 4, no consideration is given to the problem of the disturbance, which will be caused by the leak magnetic field induced by the write current when an interval between the memory cells decreases according to an increased integration degree of the memory cell array.
In this prior art reference 4, a memory array is utilized as a macro. A memory cell array structure is registered as a library and, in expanding the memory cell array, the memory cell array structure (memory macro) is repetitively arranged in the row and column directions to expand the memory cell array.
In this prior art reference 4, in the memory macro, the memory cell array is arranged on one side of the write word drivers driving the write-word/read-bit lines, and no consideration is given to how to place the memory macro when the memory cell arrays are to be arranged on the both sides of the write word line drivers for reducing the lengths of the write-word/read-bit lines.
A prior art reference 5 (U.S. Pat. No. 6,418,046) discloses a structure, in which memory cell arrays are arranged on both sides of an axis extending in the column direction with a control circuit, a row decoder and a digit line current supply being a center. Bit lines are arranged extending in the column direction in both memory cell arrays, and the digit lines in each memory cell array are arranged directing toward row decode circuitry in the central area. The digit lines and the read word lines are interconnected, respectively. By utilizing one memory cell array as a macro, it is intended to facilitate the expansion of the memory cell array. Arranging the digit line current supply in the central region allows both the memory cell arrays to share the digit line drive current supply. The digit line current is supplied only to a selected memory array. Bit line write current drive circuitry is arranged such that the current can be supplied bidirectionally to a bit line according to write data. In this prior art reference 5, however, the memory cell is formed into substantially a regular square form, and no consideration is given to the directions of a magnetization-easy axis and a magnetization-hard axis of a magneto-resistance element of the memory cell in the arrangement of the memory cell array.
A prior art reference 6 (U.S. Pat. No. 6,097,626) discloses a structure for overcoming the problem of the magnetic disturbance in the write operation, in which an unselected cell adjacent to a selected cell is supplied, during a write operation, with a canceling current in a direction opposite to that of a write current supplied to the selected cell, for preventing data inversion in the unselected adjacent memory cell due to a magnetic field induced by the write current. In this prior art reference 6, no consideration is given to a problem of increase of the leak magnetic field, which is caused by a peak current when supply of the write current starts or stops.
In constructing a system LSI such as a System On Chip (SOC), a logic and a memory are integrated on a common semiconductor chip. For arranging a memory in the SOC, a memory macro, which is already designed and registered as a library, is used in view of design efficiency. In the construction of the prior art reference 5 as described above, the memory arrays arranged on both sides of the control circuit share the digit line current supply and only expansion of the memory arrays in a single memory chip is considered. No consideration is given to how to arrange the memory and to construct the memory when embedded with a logic.
The memory macro may be configured to cover an entire memory circuit including a memory cell array as well as a row decoder, a digit line drive circuit and a bit line drive circuit. In this case, upon integration mixedly with a logic, it may become necessary to arrange the memory macros into a point-symmetrical lay-out depending on a positional relationship between the memory macros and the logic. MRAM cell stores data according to a parallel/anti-parallel relationship between the magnetization directions of the free and fixed layers of the magneto-resistance element. On the same semiconductor chip, the magnetization directions of the fixed layers of the memory cells are usually set forcedly by an external magnetic field in a wafer process, and are equal to each other. Due to a symmetrical operation of the layout of the memory macro, the relationship between the magnetization direction of the free layer relative to the magnetization direction of the fixed layer and the logical level of the write data may differ from the original relationship in the macro.
A prior art reference 7 (Japanese Patent Laying-Open No. 2000-163990) discloses a configuration, in which a logical level of storage data is selectively inverted according to a relationship between an externally applied logical address and an internal actual address (physical address) in a memory cell array. For testability, there are provided an address scramble circuit that converts an external address so as to match the logical address with the physical address, and a data scramble circuit for controlling inversion of data according to a logical or physical address. In a structure in which a memory cell is connected to one of complementary bit lines as the case of a DRAM (Dynamic Random Access Memory) cell, such a situation may occur depending on an address that externally applied logical data differs in logical value from corresponding physical data actually stored in a memory cell. The prior art reference 7 also intends to perform correctly testing even in such case. The prior art reference 7 requires the address scramble circuit and the data scramble circuit, and thus makes complicated the circuit construction. In the case where inversion/non-inversion of the data varies depending on the position of the memory cell array and the magnetization direction of the fixed layer, it is difficult to set uniquely in advance the address scramble and the data scramble.
In the conventional magnetic memory devices, as described above, it is impossible to suppress efficiently the magnetic disturbance resulting from the write peak current in writing in an increased integration degree, and an integrity cannot be maintained between the logical data (external write/read data) and the physical data (stored data in memory cells).
In a system on chip or a system LSI constructed by utilizing a memory macro, the relationship between the logical data and the magnetization direction of the free layer with respect to the fixed layer may vary depending on the positional relationship between the logic and the memory macro. This results in a problem that integrity cannot be maintained between logical data and physical data or between external write data and external read data.